1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to address buffers for semiconductor memory devices.
2. Discussion of the Related Art
Memory chip designers and users seek semiconductor memory chips capable of satisfying high density integration, high-speed operation, and low power consumption.
Generally, transistor-transistor logic (TTL) or complementary metal oxide semiconductor (CMOS) technologies have been used for chips that communicate data with dynamic random access memories (DRAMs). TTL has a noise margin narrower than that of CMOS. In particular, DRAMs connected to such chips are required to withstand variations of power supply voltage, temperature changes and the like and to perform stable operation despite noise. DRAMs are designed with the assumption that an external input signal is at a TTL level. A buffer connected to an address pin is called an address input buffer or an address buffer. Address buffers convert the external TTL signal to a CMOS signal used in the DRAM. The Address Buffer is typically used to buffer (e.g., invert) the column and row addresses that are sent via the address bus. Address selection is performed in two phases, first the row is selected, then the column.
An address input to the address buffer is called an external address, and a converted output from the address buffer is called an internal address. The internal address is input to a decoder to select a word line of memory cells having data stored therein.
A conventional address buffer circuit for buffering an external address and outputting an internal address as a buffered result signal will be described with reference to FIGS. 1 and 2.
FIG. 1 is a schematic block diagram of a conventional address buffer device.
Referring to FIG. 1, in the address buffer 1, there is an external address signal (ext.an) indicating an address input to the address buffer 1, an internal address signal (int.an) that is a buffered version of the external address signal (ext.an), and a memory control signal (con.sig) synchronized by a clock.
When the external address signal (ext.an) is input to the address buffer 1, the address buffer 1 outputs the internal address signal (int.an) as a buffered signal.
The memory control signals (con.sig) are signals that are combined to produce a command for controlling the operation of a semiconductor memory device. That is, the memory control signals (con.sig) are signals for accessing memory cells in the semiconductor memory device through their logical combination. Generally, the memory control signals include a row address strobe, a column address strobe, a write enable signal and the like.
In address multiplexing (mainly used in DRAMs), the address is broken up into two pieces, a row address (most significant digits of address, e.g., 10 bits) and a column address (least significant digits of address, e.g., 12 bits). The address is strobed over in these two components. (This saves expensive external pins since fewer (e.g., 12) address lines are needed (e.g., instead of 22.) To distinguish between the column and the write address, the CAS* and RAS* (column address strobe and row address strobe) signals are used.
Thus, in address multiplexing, an address is input and controlled by a row address strobe (RAS) and a column address strobe (CAS). (Hereinafter, for convenience of illustration, it is assumed that the row address strobe and the column address strobe indicate that are inverted signals, RASB and CASB respectively). In particular, to shorten an access time, the column address in DRAMs is not under direct control of the column address strobe and, instead, the column address responds to a signal indicating that input of a row address is completed by the row address strobe. Memory control signals (con.sig), such as the row address strobe, the column address strobe, write enable signal (WE) and the like, cause standby, power down, refresh and the like to occur in memory cells of the semiconductor memory device. (For convenience of illustration, it is assumed that the write enable signal is an inverted signal, WEB.) At this time, even though the memory control signals (con.sig) are logically combined to produce a command for controlling the operation of the semiconductor memory device, there exists a state where no operation occurs in the memory cells. This is called the ‘no operation’ command (NOP).
The ‘NO OPERATION’ command (NOP) prevents unwanted commands from being registered during idle or wait states (e.g., when CS is unselected). For example, when the row address strobe and the column address strobe have a logic value of ‘1’, the memory device enters ‘no operation’ command.
This ‘no operation’ command is generally specified in a specification of a semiconductor memory device.
In the ‘no operation’ command, there is no operation occurring in the memory device, but the internal address signal (int.an) continues to be output. This results in power consumption due to current flowing through the address buffer 1.
Further, the internal address signal (int.an), which is buffered and output in the address buffer 1, is input to all chips, resulting in increased power consumption.
To reduce power consumption in the semiconductor memory device, a method has been used that performs a separate logical operation at a subsequent stage of the address buffer 1, allowing a buffered signal from the address buffer 1 to be selected by a chip select signal.
FIG. 2 is a schematic diagram of an address buffer circuit in which NAND operation is performed on a chip select signal and a buffered signal from an address buffer in FIG. 1, allowing the buffered signal from the address buffer to be selected by a chip select signal.
Referring to FIG. 2, a NAND gate 2 for performing NAND operation with a chip select signal (cs) is connected to a subsequent stage of an address buffer in FIG. 1.
A process will be described which inputs and buffers an external address signal (ext.an) from an address pin (not shown) to the address buffer 11, and then, outputs an internal address signal (int.an).
An external address signal (ext.an) is first input to the address buffer 11. The NAND gate 2 performs NAND operation on the buffered signal (m.an) from the address buffer 11 and on a chip select signal (cs). A result of the NAND operation is an internal address signal (int.an). To select one desired word line, the internal address signal (int.an) is pre-decoded prior to being input to a decoder (not shown).
For example, when a logic value of the chip select signal (cs) is ‘0’, the output of the NAND gate 2 becomes ‘1’ whether a logic value of an output signal (m.an) from the address buffer 11 is ‘1’ or ‘0’. Accordingly, the internal address (int.an) becomes ‘1’. That is, by inputting the chip select signal (cs) at ‘0’, it is possible to control the output signal from the address buffer 11. The logic value ‘0’ is indicated when the voltage level is low and the logic value ‘1’ is indicated when the voltage level is high. No current flows through a non-selected chip, reducing power consumption.
In the above-described case, however, power consumption in the address buffer is not reduced since the address buffer 11 is not under direct control. Thus, there is a limitation in using a chip select signal (cs) at a subsequent stage of the address buffer to reduce power consumption.
Further, in the ‘no operation’ state (NOP command) in which no command based on memory control signals is provided to memory cells of the semiconductor memory device, the address buffer still buffers and outputs the internal address signal. Thus, unnecessary current still flows, increasing power consumption in the semiconductor memory device.